View LTC4230_182522.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FEATURES
s s
LTC4230 Triple Hot Swap Controller with Multifunction Current Control DESCRIPTIO
The LTC(R)4230 is a 3-channel Hot SwapTM controller that allows a board to be safely inserted and removed from a live backplane. Internal high side switch drivers control the gates of external N-channel MOSFETs for supply voltages ranging from 1.7V to 16.5V. The LTC4230 provides soft-start and inrush current limiting during the programmable start-up period. On-chip current limit comparators provide dual level circuit breaker protection. The slow comparators trip at VCCn - 50mV and activate in 10s or are programmed by an external filter capacitor. The fast comparators trip at VCCn - 150mV and typically respond in 500ns. Each FBn pin monitors its own output supply voltage and signals its RESET pin. The ON pin turns the chip on and off and can be used for a reset function. The LTC4230 also provides additional functions including fault indication, autoretry or latchoff modes, programmable current limit response time based on the FAULT and FILTER pins' functionality.
, LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation.
s
s s s s s s s s s
Allows Safe Board Insertion and Removal from a Live Backplane Controls Three Supply Voltages from 1.7V to 16.5V with VCC1 VCC2 VCC3 Programmable Soft-Start with Inrush Current Limiting, No External Gate Capacitor Required Faster Turn-Off Time with No Gate Capacitor Dual Level Overcurrent Fault Protection Programmable Overcurrent Response Time Programmable Overvoltage Protection Automatic Retry or Latched Mode Operation Independent N-Channel FET High Side Drivers User-Programmable Supply Voltage Power-Up Rate FBn Pin Monitors VOUTn and Signals RESETn Glitch Filter Eliminates Spurious RESETn Signals
APPLICATIO S
s s
s
Electronic Circuit Breaker Hot Board Insertion and Removal (Either On Backplane or On Removable Card) Industrial High Side Switch/Circuit Breaker
TYPICAL APPLICATIO
BACKPLANE CONNECTOR (FEMALE) VCC1 3.3V VCC2 2.5V VCC3 1.8V PCB EDGE CONNECTOR (MALE) LONG LONG LONG Z1***
3-Channel Hot Swap Controller
RSENSE1 0.007 Q1 IRF7413 RSENSE2 0.007 Q2 IRF7413 RSENSE3 0.007 RX2 10 Q3 IRF7413 VOUT1 3.3V 5A VOUT2 2.5V 5A VOUT3 1.8V 5A R8 5.1k R9 12k RESET 3 2 R10 11k R11 12k RESET 2 GND RESET 1 TIMER FILTER FB1 10 19 9 R12 18k R13 12k
4230 TA01
RX1 10 CX1 100nF RX3 10 CX3 100nF Z3*** CX2 100nF
Z2***
6 VCC1
7 SENSE 1
8 GATE 1
16 VCC2
17 SENSE 2
18
5
GATE 2 VCC3
SENSE 3 GATE 3 FB3 1
PCB CONNECTION SENSE SHORT R1 10k R2 10k 15 FAULT GND SHORT LONG 13 14 12 11 * SYSTEM ON TIME: 6.2ms **CIRCUIT BREAKER RESPONSE TIME: 19.5s ***OPTIONAL Z1, Z2, Z3: SMAJ10 CTIMER* 0.1F CFILTER** 15pF LTC4230 ON FAULT
U
U
U
4
3 R7 10k
RESET 3
FB2
20
R6 10k
R5 10k RESET 2 RESET 1
4230f
1
LTC4230
ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW FB3 RESET 3 GATE 3 SENSE 3 VCC3 VCC1 SENSE 1 GATE 1 RESET 1 1 2 3 4 5 6 7 8 9 20 FB2 19 RESET 2 18 GATE 2 17 SENSE 2 16 VCC2 15 ON 14 GND 13 FAULT 12 TIMER 11 FILTER
Supply Voltage (VCCn) ............................................. 17V SENSEn Pins ............................... - 0.3V to (VCC + 0.3V) FBn, ON Pins ............................... - 0.3V to (VCC + 0.3V) TIMER Pin ...................................................- 0.3V to 2V GATEn Pins ........................... Internally Limited (Note 3) RESETn, FAULT, FILTER Pins ....................- 0.3V to 17V Operating Temperature Range LTC4230C ............................................... 0C to 70C LTC4230I ............................................ - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC4230CGN LTC4230IGN
FB1 10
GN PACKAGE 20-LEAD PLASTIC SSOP
TJMAX = 125C, JA = 95C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL VCC PARAMETER Supply Voltage (VCC1) Supply Voltage (VCC2) Supply Voltage (VCC3) Supply Current (ICC1) Supply Current (ICC2) Supply Current (ICC3) Undervoltage Lockout , Channel 1 Undervoltage Lockout , Channel 2 Undervoltage Lockout , Channel 3 Undervoltage Lockout Hysteresis, Channel 1 Undervoltage Lockout Hysteresis, Channel 2 Undervoltage Lockout Hysteresis, Channel 3 FBn Pin Input Current ON Pin Input Current Input Current for SENSEn Circuit Breakern Trip Voltage GATEn Pull-Up Current Normal GATEn Pull-Down Current Fast GATEn Pull-Down Curent ILEAK RESETn Leakage Current
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VCC1 = 3.3V, VCC2 = 2.5V,VCC3 = 1.8V unless otherwise noted. (Note 2)
CONDITIONS VCC2 VCC1 VCC3 (VCC1 - 1V) ON = VCC1, FB1 = High ON = VCC1, FB2 = High ON = VCC1, FB3 = High VCC1 Low to High Transition VCC2 Low to High Transition VCC3 Low to High Transition
q q q q q q q q q
MIN 2.700 2.375 1.700
TYP
MAX 16.5 16.5 15.5
UNITS V V V mA A A V V V mV mV mV
ICC
1.8 75 65 2.15 1.98 1.09 2.35 2.15 1.19 100 45 35
3 150 150 2.52 2.32 1.29
VLKO1 VLKO2 VLKO3 VLKOHST1 VLKOHST2 VLKOHST3 IIN, FBn IIN, ON IIN, SENSEn VCB(FAST) VCB(SLOW) IGATEn, UP IGATEn, DN
0V VFBn VCCn 0V VON VCC1 0V VSENSEn VCCn Fast Comparator Slow Comparator Charge Pump On, 0 VGATEn < 0.2V ON Low, VGATEn = 5V FAULT Latched and Circuit Breaker Tripped or in UVLO, VGATEn = 5V VRESETn = 15V, Pull-Down Device Off
q q q q q q
0.1 0.1 0.1 135 40 -12.5 150 50 -10 200 16
10 10 15 165 60 -6.5
q
0.1
2.5
2
U
A A A mV mV A A mA A
4230f
W
U
U
WW
W
LTC4230
ELECTRICAL CHARACTERISTICS
SYMBOL VGATEn PARAMETER External N-Channel Gate Drive
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VCC1 = 3.3V, VCC2 = 2.5V,VCC3 = 1.8V unless otherwise noted. (Note 2)
CONDITIONS VGATE1, 2 - VCC1, 2 (for VCC1, 2 = 2.7V, VCC3 = VCC1 - 1V) VGATE3 - VCC3 (for VCC1, 2 = 2.7V, VCC3 = VCC1 - 1V) VGATE1, 2 - VCC1, 2 (for VCC1, 2 = 3.3V, VCC3 = VCC1 - 1V) VGATE3 - VCC3 (for VCC1, 2 = 3.3V, VCC3 = VCC1 - 1V) VGATEn - VCCn (for VCC1, 2 = 5V, VCC3 = VCC1 - 1V) VGATEn - VCCn (for VCC1, 2 = 12V or 15V, VCC3 = VCC1 - 1V)
q q q q q q
MIN 4.5 5.5 5 6 9 7
TYP
MAX 8 9 10 11 16 18
UNITS V V V V V V V
VGATEn, 0V VFBn VFBn VFBn, HST VONHI VONLO VONHST IFILTER VFILTER VFILTERHST ITMR
GATEn Overvoltage Lockout Threshold FBn Low Threshold Voltage FBn Line Regulation FBn Hysteresis ON High Threshold Voltage ON Low Threshold Voltage ON Hysteresis FILTER Pull-Up Current FILTER Pull-Down Current FILTER Threshold FILTER Threshold Hysteresis TIMER Pull-Up Current TIMER Pull-Down Current TIMER Threshold FAULT Low Threshold Voltage FAULT Hysteresis FAULT Pull-Up Current Output Low Voltage Output Low Voltage Fast COMPn Trip to GATEn Discharging Slow Comparator Trip to FILTER High and FAULT Latched FILTER Comparator Trip to GATEn Discharging FAULT Low to GATE Discharging Circuit Breaker Reset Time Turn-Off Time IFAULT = 1.6mA, VCC1 = 5V IRESETn = 1.6mA, VCC1 = 5V VCB = 0mV to 200mV Step VCB = 0mV to 100mV Step, FILTER Floating 10nF at FILTER Pin to GND VFILTER = 0V to 5V VFAULT = 5V to 0V ON Held Low to Guarantee FAULT High ON Goes Low to GATEn Off
q q q q
0.25 FBn High to Low Transition 2.7V VCC1 16.5V ON Low to High Transition ON High to Low Transition During Slow Fault Condition During Normal and Reset Conditions Latched Off Threshold, FILTER Low to High TIMER On TIMER Off, VFAULT = Low VTIMER = 1.5V TIMER Low to High TIMER High to Low FAULT High to Low FAULT Low to High
q q q q q q q
1.209
1.234 0.5 3
1.259
V mV mV
1.250 1.172 - 2.5 7 1.10 - 23 0.9 1.172 1.172 - 2.5
1.314 1.234 80 -2 10 1.26 -70 - 20 1.6 2.5 1.234 0.3 1.234 50 -2 0.19 0.19 0.5 10 7 8
1.380 1.270 -1.3 13 1.42 -17 2.3 1.27 0.5 1.27 - 1.5 0.4 0.4 1
V V mV A A V mV A A mA V V V mV A V V s s
q q q
q q q q q
VTMR VFAULT VFAULT, HST IFAULT, UP VOLFAULT VOLRESETn tGATEFC tFAULTSC tOVPFTR tEXTFAULT tRESET tOFF
12 12 4.5 30
ms s s s s
1.5
3 15 8
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All current into device pins is positive; all current out of device pins is negative; all voltages are referenced to ground unless otherwise specified.
Note 3: An internal zener at the GATEn pin clamps the charge pump voltage to a typical maximum operating voltage of 26V. External overdrive of the GATEn pin beyond the internal zener voltage may damage the part. The GATEn capacitance must be < 0.15F at maximum VCC. If a lower GATEn pin voltage is desired, use an external zener diode.
4230f
3
LTC4230 TYPICAL PERFOR A CE CHARACTERISTICS
Channel 1 Supply Current vs VCC1 Supply Voltage
8 7 SUPPLY CURRENT (mA) 6 5 4 3 2 1 0 2 4 8 10 12 14 VCC1 SUPPLY VOLTAGE (V) 6 16 18 -40C 25C 85C VCC2 = 2.5V VCC3 = 1.8V SUPPLY CURRENT (mA) 0.6 -40C 0.5 0.4 CHANNEL 3 0.3 CHANNEL 2 0.2 0.1 0 25C 85C
UNDERVOLTAGE LOCKOUT THRESHOLD VOLTAGE (V)
FBn Pin Input Current vs Temperature
5 VFBn = 5V 6
SENSEn INPUT CURRENT (nA)
FBn PIN INPUT CURRENT (nA)
ON PIN INPUT CURRENT (nA)
4
3
2
1
0 -75 -50 -25
0 25 50 75 100 125 150 TEMPERATURE (C)
4230 G04
ON Threshold vs Temperature
1.36
FAST COMPARATOR TRIP VOLTAGE (mV)
ON THRESHOLD VOLTAGE (V)
1.34 1.32 1.30 1.28 1.26 1.24
VCC1 = 3.3V VCC2 = 2.5V VCC3 = 1.8V ON PIN HIGH
151.5 151.0 150.5 150.0 149.5 149.0 148.5 148.0
-40C 25C 85C
SLOW COMPARATOR TRIP VOLTAGE (mV)
ON PIN LOW
1.22 -75 -50 -25
0 25 50 75 100 125 150 TEMPERATURE (C)
4230 G07
4
UW
4230 G01
Channels 2 and 3 Supply Current vs Supply Voltage
2.5
UVLO Threshold Voltage vs Temperature
2.2 VCC1 HIGH 1.9 VCC1 LOW VCC2 HIGH 1.6 VCC2 LOW VCC3 HIGH 1.3 VCC3 LOW
2
4
6 8 10 12 14 SUPPLY VOLTAGE (V)
16
18
1.0 -75 -50 -25
0 25 50 75 100 125 150 TEMPERATURE (C)
4230 G03
4230 G02
ON Pin Input Current vs Temperature
100 VON = 5V 5 4 3 2 1 0 -75 -50 -25 90 80 70 60 50 40 30 20 10 0 25 50 75 100 125 150 TEMPERATURE (C)
4230 G05
SENSEn Input Current vs Temperature
VSENSEn = 5V
0 -75 -50 -25
0 25 50 75 100 125 150 TEMPERATURE (C)
4230 G06
Fast Comparator Threshold vs VCC1 Supply Voltage
152.0 52.0
Slow Comparator Threshold vs VCC1 Supply Voltage
-40C 51.5 51.0 50.5 50.0 49.5 49.0 25C 85C
0
2
4 6 8 10 12 14 VCC1 SUPPLY VOLTAGE (V)
16
18
0
2
4 6 8 10 12 14 VCC1 SUPPLY VOLTAGE (V)
16
18
4230 G08
4230 G09
4230f
LTC4230 TYPICAL PERFOR A CE CHARACTERISTICS
Normal GATEn Pull-Down Current vs VCC1 Supply Voltage
280 FAST PULL-DOWN CURRENT (mA) GATE PULL-DOWN CURRENT (A) 260 240 220 200 180 160 140 120 2 4 8 10 12 14 VCC1 SUPPLY VOLTAGE (V) 6 16 18 VCC2 = 2.5V VCC3 = 1.8V VGATEn = 2.5V 85C -40C 25C 20
IGATE CURRENT (A)
VGATEn - VCCn vs VCC1 Supply Voltage
16 14 VGATE VOLTAGE (V) 12 VGATE1 = VGATE2 10 8 6 4 2 0 2 4 8 10 12 14 VCC1 SUPPLY VOLTAGE (V) 6 16 18 VCC2 = VCC1 VCC3 = VCC1 - 1V VGATE3
VGATE - VCC1 VOLTAGE (V)
GATE OVERVOLTAGE LOCKOUT THRESHOLD (V)
GATEn Overvoltage Lockout Threshold vs VCC1 Supply Voltage
GATE OVERVOLTAGE LOCKOUT THRESHOLD (V) 0.5
VFB THRESHOLD VOLTAGE (V)
FB THRESHOLD VOLTAGE (V)
VCC2 = 2.5V VCC3 = 1.8V 0.4
0.3
0.2
0.1
0
0
2
4 6 8 10 12 14 VCC1 SUPPLY VOLTAGE (V)
UW
4230 G10 4230 G13
Fast GATEn Pull-Down Current vs VCC1 Supply Voltage
12 11 -40C 10 9 8 7 6
GATEn Output Source Current (Pull-Up) vs VCC1 Supply Voltage
85C
18
25C
16
25C 85C VCC2 = 2.5V VCC3 = 1.8V VGATEn = 5V 0 2 4 6 8 10 12 14 VCC1 SUPPLY VOLTAGE (V) 16 18
-40C
14
12
10
0
2
4 6 8 10 12 14 VCC1 SUPPLY VOLTAGE (V)
16
18
4230 G11
4230 G12
VGATE1 - VCC1 vs Temperature
16 14 12 10 8 VCC1 = 3.3V 6 VCC1 = 2.7V 4 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C)
4230 G14
GATEn Overvoltage Lockout Threshold vs Temperature
0.5 VCC1 = 3.3V VCC2 = 2.5V VCC3 = 1.8V
VCC1 = 5V VCC1 = 12V VCC1 = 15V
0.4
0.3
0.2
0.1
0 -75 -50 -25
0 25 50 75 100 125 150 TEMPERATURE (C)
4230 G15
VFBn Threshold Voltage vs Temperature
1.239 1.238 1.237 1.236 1.235 1.234 1.233 1.232 -75 -50 -25 1.233 0 25 50 75 100 125 150 TEMPERATURE (C)
4230 G17
VFBn Threshold Voltage vs VCC1 Supply Voltage
1.238
VCC1 = 3.3V VCC2 = 2.5V VCC3 = 1.8V VFBn HIGH
1.237
FB HIGH
1.236
1.235 FB LOW
VFBn LOW
1.234
16
18
0
2
4 6 8 10 12 14 VCC1 SUPPLY VOLTAGE (V)
16
18
4230 G16
4230 G18
4230f
5
LTC4230 TYPICAL PERFOR A CE CHARACTERISTICS
FILTER Pull-Up Current vs Temperature
-1.6
IFILTER CURRENT LOW (A)
-1.8
VCC1 = 2.7V
11.2
IFILTER CURRENT (A)
VCC1 = 5V
VCC1 = 16.5V 10.4
VCC1 = 5V
IFILTER THRESHOLD VOLTAGE (V)
-2.0 VCC1 = 3.3V -2.2 VCC1 = 16.5V VCC1 = 12V
-2.4
VCC2 = 2.5V VCC3 = 1.8V 0 25 50 75 100 125 150 TEMPERATURE (C)
4230 G19
-2.6 -75 -50 -25
FAULT Threshold Voltage vs VCC1 Supply Voltage
1.29 -40C HIGH THRESHOLD FAULT PULL-UP CURRENT (A) 85C 1.27 25C 1.26 1.25 1.24 1.23 -40C LOW THRESHOLD 85C 0 2 4 6 8 10 12 14 VCC1 SUPPLY VOLTAGE (V) 16 18 1.5 2.3 2.5
FAULT THRESHOLD VOLTAGE (V)
TIMER PULL-UP CURRENT (A)
1.28
TIMER Pull-Down Current (After Second Cycle) vs VCC1 Supply Voltage
2.0 TIMER PULL-DOWN CURRENT (mA) TIMER PULL-DOWN CURRENT (A) 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 0 2 4 6 8 10 12 14 VCC1 SUPPLY VOLTAGE (V) 16 18 -40C 25C 85C 9 8 7 6 5 4 3 2 1 0
25C 85C
TIMER HIGH THRESHOLD (V)
6
UW
25C
4230 G22 4230 G25
FILTER Pull-Down Current vs Temperature
12.0
1.30 1.28 1.26 1.24 1.22 1.20 1.18 1.16
FILTER Threshold Voltage vs Temperature
VCC1 = 3.3V VCC1 = 5V VCC1 = 12V VCC1 = 2.7V
VCC1 = 16.5V IFILTER HIGH VCC1 = 2.7V IFILTER LOW VCC2 = 2.5V VCC3 = 1.8V VCC1 = 16.5V VCC1 = 3.3V VCC1 = 5V VCC1 = 12V
9.6 VCC1 = 12V 8.8 VCC2 = 2.5V VCC3 = 1.8V VCC1 = 2.7V
VCC1 = 3.3V
8.0 -75 -50 -25
0 25 50 75 100 125 150 TEMPERATURE (C)
4230 G20
1.14 -75 -50 -25
0 25 50 75 100 125 150 TEMPERATURE (C)
4230 G21
FAULT Pull-Up Current vs VCC1 Supply Voltage
23 85C 22 21 20
TIMER Pull-Up Current (During First Cycle) vs VCC1 Supply Voltage
85C
25C 2.1 -40C 1.9
25C 19 18 17 -40C
1.7
0
2
4 6 8 10 12 14 VCC1 SUPPLY VOLTAGE (V)
16
18
0
2
4 6 8 10 12 14 VCC1 SUPPLY VOLTAGE (V)
16
18
4230 G23
4230 G24
TIMER Fast Pull-Down (End of the First Cycle) Current vs VCC1 Supply Voltage
1.237 VTIMER = 1.5V -40C 1.236 1.235 1.234 1.233 1.232 1.231 1.230
TIMER High Threshold vs VCC1 Supply Voltage
85C 25C
-40C
0
2
4 6 8 10 12 14 VCC1 SUPPLY VOLTAGE (V)
16
18
0
2
4 6 8 10 12 14 VCC1 SUPPLY VOLTAGE (V)
16
18
4230 G26
4230 G27 4230f
LTC4230 TYPICAL PERFOR A CE CHARACTERISTICS
TIMER Low Threshold vs VCC1 Supply Voltage
0.32 0.25
TIMER LOW THRESHOLD (V)
0.31 25C 85C 0.30 -40C
VOL VOLTAGE (V)
VOL VOLTAGE (V)
0.29
0.28
0
2
4 6 8 10 12 14 VCC1 SUPPLY VOLTAGE (V)
Fast Comparator Response Time vs VCC1 Supply Voltage
SLOW COMPARATOR RESPONSE TIME (s) 650 FAST COMPARATOR RESPONSE TIME (s) 600 85C 550 25C 500 450 400 350 300 -40C
14 13 12
FILTER COMPARATOR RESPONSE TIME (s)
0
2
4 6 8 10 12 14 VCC1 SUPPLY VOLTAGE (V)
FAULT Low to GATEn Discharging vs VCC1 Supply Voltage
5
FAULT LOW TO GATEn DISCHARGING (s)
CIRCUIT BREAKER RESET TIME (s)
4
85C 25C
TURN-OFF TIME (s)
3
-40C
2
1
0
0
2
4 6 8 10 12 14 VCC1 SUPPLY VOLTAGE (V)
UW
16 16
4230 G31
VOL (RESETn, FAULT) vs VCC1 Supply Voltage
0.25
VOL (RESETn, FAULT) vs Temperture
0.20
0.22
0.15
0.19
0.10
0.16
0.05
0.13
18
0
0
2
4 6 8 10 12 14 VCC1 SUPPLY VOLTAGE (V)
16
18
0.10 -75 -50 -25
0 25 50 75 100 125 150 TEMPERATURE (C)
4230 G30
4230 G28
4230 G29
Slow Comparator Response Time (FILTER Floating) vs VCC1 Supply Voltage
10
FILTER Comparator Response Time vs VCC1 Supply Voltage
9
85C 25C
25C 11 10 9 8 7 6 0 2
85C
-40C
8
-40C
7
18
4 6 8 10 12 14 VCC1 SUPPLY VOLTAGE (V)
16
18
6
0
2
4 6 8 10 12 14 VCC1 SUPPLY VOLTAGE (V)
16
18
4230 G32
4230 G33
Circuit Breaker Reset Time vs VCC1 Supply Voltage
20 11 10 9
Turn-Off Time vs VCC1 Supply Voltage
18
85C 25C
16
85C
8 7 6 5
-40C
14
25C -40C
12
16
18
10
0
2
4 6 8 10 12 14 VCC1 SUPPLY VOLTAGE (V)
16
18
0
2
4 6 8 10 12 14 VCC1 SUPPLY VOLTAGE (V)
16
18
4230 G34
4230 G35
4230 G36
4230f
7
LTC4230
PI FU CTIO S
FB3 (Pin 1): The FB3 (Feedback) pin is an input to the FBCOMP3 comparator which monitors the VCC3 output supply voltage through an external resistor divider. If VFB3 < 1.234V, RESET 3 pin pulls low. An internal glitch filter at FBCOMP3's output prevents triggering a reset condition due to negative voltage transients. If VFB3 > 1.237V, RESET 3 pin goes high after exiting undervoltage lockout. RESET 3 (Pin 2): An open-drain N-channel device whose source connects to GND (Pin 14). This pin pulls low if the voltage at FB3 (Pin 1) falls below the FB3 threshold (1.234V). This pin requires an external pull-up resistor to VOUT3. If an undervoltage lockout condition occurs, RESET 3 pulls low independently of FB3 to prevent false glitches. GATE 3 (Pin 3): The output signal at this pin is the high side gate drive for Channel 3's external N-channel MOSFET pass transistor. An internal charge pump produces a 4.5V (minimum) to 18V (maximum) gate drive voltage for VCC1 supply voltages from 2.7V to 16.5V, respectively. As shown in the Block Diagram for each channel, an internal charge pump supplies a 10A gate current and sufficient gate voltage drive to the external MOSFET. The internal charge pump produces a minimum 4.5V gate drive for VCC1 < 4.75V. For VCC1 > 4.75V, the minimum gate voltage drive is 9V. For VCC1 12V, the minimum gate voltage drive is 7V which is set by an internal zener diode clamp connected between the GATE 3 pin and GND. SENSE 3 (Pin 4): Circuit Breaker Sense Pin for Channel 3. With a sense resistor placed in the power path between VCC3 and SENSE 3, Channel 3's electronic circuit breaker trips if the voltage across the sense resistor (VCC3 - VSENSE3) exceeds the thresholds set internally for SLOW COMP3 and FAST COMP3, as shown in the Block Diagram. The threshold for SLOW COMP3 is VCB(SLOW) = 50mV, and the electronic circuit breaker trips if the voltage across RSENSE3 exceeds 50mV for 10s, or for the time delay programmed by CFILTER. To adjust SLOW COMP3's delay, please refer to the section on Adjusting SLOW COMPn's Response Time. Under transient conditions where large step current changes can and do occur over shorter periods of time, a second (fast) comparator instead trips the electronic circuit breaker. The threshold for FAST COMP3 is set at VCB(FAST) = 150mV, and the circuit breaker trips if the voltage across the RSENSE3 exceeds 150mV for more than 500ns. FAST COMP3's delay is fixed in the LTC4230 and cannot be adjusted. To disable Channel 3's electronic circuit breaker, connect the VCC3 and SENSE 3 pins together. VCC3 (Pin 5): Positive Supply Input for Channel 3. VCC3 operates from 1.7V to 15.5V (VCC3 VCC1 - 1V) and its supply current, ICC3, is typically 65A. The master UVLO circuit disables all three GATEn outputs of the LTC4230 until the voltage at VCC3 exceeds 1.19V. VCC1 (Pin 6): This is the positive supply input to the LTC4230, the power supply input for Channel 1, and the power supply input for all three internal charge pumps. The LTC4230 operates from 2.7V to 16.5V, and the ICC1 supply current is typically 1.8mA. The master UVLO circuit disables all three GATEn outputs of the LTC4230 if VCC1 is less than 2.35V. The internal charge pump outputs are enabled when V CC1 > 2.35V, V CC2 > 2.15V, and VCC3 > 1.19V. SENSE 1 (Pin 7): Circuit Breaker Sense Pin for Channel 1. With a sense resistor placed in the power path between VCC1 and SENSE 1, Channel 1's electronic circuit breaker trips if the voltage across the sense resistor (VCC1 - VSENSE1) exceeds the thresholds set internally for SLOW COMP1 and FAST COMP1, as shown in the Block Diagram. The threshold for SLOW COMP1 is VCB(SLOW) = 50mV, and the electronic circuit breaker trips if the voltage across RSENSE1 exceeds 50mV for 10s, or for the time delay programmed by CFILTER. To adjust SLOW COMP1's delay, please refer to the section on Adjusting SLOW COMPn's Response Time. Under transient conditions where large step current changes can and do occur over shorter periods of time, a second (fast) comparator instead trips the electronic circuit breaker. The threshold for FAST COMP1 is set at VCB(FAST) = 150mV, and the circuit breaker trips if the voltage across the RSENSE1 exceeds 150mV for more than 500ns. FAST COMP1's delay is fixed in the LTC4230 and cannot be adjusted. To disable Channel 1's electronic circuit breaker, connect the VCC1 and SENSE 1 pins together.
4230f
8
U
U
U
LTC4230
PI FU CTIO S
GATE 1 (Pin 8): The output signal at this pin is the high side gate drive for Channel 1's external N-channel FET pass transistor. An internal charge pump produces a 4.5V (minimum) to 18V (maximum) gate drive voltage for supplies in the range of 2.7V VCC1 16.5V, respectively. As shown in the Block Diagram, each channel's internal charge pump is powered by VCC1 and supplies a 10A gate current and sufficient gate voltage drive to the external FET. The internal charge pump produces a minimum 4.5V gate voltage drive for VCC1 < 4.75V. For VCC1 > 4.75V, the minimum gate voltage drive is 9V. For VCC1 12V, the minimum gate voltage drive is 7V which is set by an internal zener diode clamp connected between the GATE 1 pin and GND. RESET 1 (Pin 9): An open-drain N-channel device whose source connects to GND (Pin 14). This pin pulls low if the voltage at FB1 (Pin 10) falls below the FB1 threshold (1.234V). During the start-up cycle, RESET 1 goes high impedance at the end of the second timing cycle after FB1 goes above the FB1 threshold. This pin requires an external pull-up resistor to VOUT1. If an undervoltage lockout condition occurs, RESET 1 pulls low independently of FB1 to prevent false glitches. FB1 (Pin 10): The FB1 (Feedback) pin is an input to the FBCOMP1 comparator which monitors the VCC1 output supply voltage through an external resistor divider. If VFB1 < 1.234V, RESET 1 pin pulls low. An internal glitch filter at FBCOMP3's output prevents triggering a reset condition due to negative voltage transients. If VFB1 > 1.237V after the second timing cycle, RESET 1 goes high. FILTER (Pin 11): Overcurrent Fault Timing Pin and Overvoltage Fault Set Pin. With a capacitor connected from this pin to ground, the response time of all three SLOW COMP comparators can be adjusted. Note that the response time of the SLOW COMP comparators cannot be adjusted individually. TIMER (Pin 12): A capacitor connected from this pin to GND sets the LTC4230's system timing. The LTC4230's initial and second start-up timing cycles and its discharge mode delay time are controlled by this capacitor. FAULT (Pin 13): FAULT is a dual function (an input and an output) internal to the LTC4230. Connected to this pin are an analog comparator (COMP6) and an open-drain N-channel FET. During normal operation, if COMP6 is driven below 1.234V, all electronic circuit breakers trip and each GATE pin pulls low. Referring to the Block Diagram, FAULT incorporates an internal 2A current source pull up. This allows the LTC4230 to begin a second timing cycle (VFAULT > 1.284V) and start up properly. This also allows the use of the FAULT pin as a status output. Under normal operating conditions, the FAULT output is a logic high. Two conditions cause an active low on FAULT: 1) the LTC4230's electronic circuit breakers trip because of an output short circuit (VOUTn = 0V) or because of a fast output overcurrent transient (FAST COMPn trips its circuit breaker); or 2) VFILTER > 1.26V. The FAULT output is driven to logic low and is latched logic low until the ON pin is driven to logic low for 30s (the tRESET duration). GND (Pin 14): Device Ground Connection. Connect this pin to the system's analog ground plane. ON (Pin 15): An active high signal used to enable or disable LTC4230 operation. As shown in the LTC4230 Block Diagram, COMP1's threshold is set at 1.234V and its hysteresis is set at 80mV. If a logic high signal is applied to the ON pin (VON > 1.314V), the first timing cycle begins if an overvoltage condition does not exist on any of the GATEn pins (Pins 3, 8, and 18). If a logic low signal is applied to the ON pin (VON < 1.234V), each GATEn pin is pulled low by an internal, dedicated 200A current sink. The ON pin can also be used to reset all three electronic circuit breakers. If the ON pin is cycled low for more than 1 tRESETn(MAX) period and then high following a circuit breaker trip, all internal circuit breakers are reset and the LTC4230 begins a new start-up cycle. VCC2 (Pin 16): Positive Supply Input for Channel 2. VCC2 operates from 2.375V to 16.5V and its supply current, ICC2, is typically 75A. The master UVLO circuit disables all three GATEn outputs of the LTC4230 until the voltage at VCC2 exceeds 2.15V.
U
U
U
4230f
9
LTC4230
PI FU CTIO S
SENSE 2 (Pin 17): Circuit Breaker Sense Pin for Channel 2. With a sense resistor placed in the power path between VCC2 and SENSE 2, Channel 2's electronic circuit breaker trips if the voltage across the sense resistor (VCC2 - VSENSE2) exceeds the thresholds set internally for SLOW COMP2 and FAST COMP2, as shown in the Block Diagram. The threshold for SLOW COMP2 is VCB(SLOW) = 50mV and the electronic circuit breaker trips if the voltage across RSENSE2 exceeds 50mV for 10s, or for the time delay programmed by CFILTER. To adjust SLOW COMP2's delay, please refer to the section on Adjusting SLOW COMPn's Response Time. Under transient conditions where large step current changes can and do occur over shorter periods of time, a second (fast) comparator instead trips the electronic circuit breaker. The threshold for FAST COMP2 is set at VCB(FAST) = 150mV, and the circuit breaker trips if the voltage across the RSENSE2 exceeds 150mV for more than 500ns. FAST COMP2's delay is fixed in the LTC4230 and cannot be adjusted. To disable Channel 2's electronic circuit breaker, connect the VCC2 and SENSE 2 pins together. GATE 2 (Pin 18): The output signal at this pin is the high side gate drive for Channel 2's external N-channel FET pass transistor. An internal charge pump produces a 4.5V (minimum) to 18V (maximum) gate drive voltage for VCC1 supply voltages from 2.7V to 16.5V, respectively. As shown in the Block Diagram for each channel, an internal charge pump supplies a 10A gate current and sufficient gate voltage drive to the external FET. The internal charge pump produces a minimum 4.5V gate drive for VCC1 < 4.75V. For VCC1 > 4.75V, the minimum gate voltage drive is 9V. For VCC1 12V, the minimum gate voltage drive is 7V which is set by an internal zener diode clamp connected between the GATE 2 pin and GND. RESET 2 (Pin 19): An open-drain N-channel device whose source connects to GND (Pin 14). This pin pulls low if the voltage at FB2 (Pin 20) falls below the FB2 threshold (1.234V). This pin requires an external pull-up resistor to VOUT2. If an undervoltage lockout condition occurs, the RESET 2 pin pulls low independently of FB2 to prevent false glitches. FB2 (Pin 20): The FB2 (Feedback) pin is an input to the FBCOMP2 comparator which monitors the VCC2 output supply voltage through an external resistor divider. If VFB2 < 1.234V, RESET 2 pulls low. An internal glitch filter at FBCOMP3's output prevents triggering a reset condition due to negative voltage transients. If VFB2 > 1.237V, RESET 2 pin goes high after exiting undervoltage lockout.
10
U
U
U
4230f
LTC4230
BLOCK DIAGRA
SENSE 1 7 VCC1 150mV
RESET 1 9 MR1
SENSE 2 17 VCC2 150mV
RESET 2 19 MR2
SENSE 3 4 FB3 1 RESET 3 2
W
VCC1 CHARGE PUMP 1 CHARGE PUMP 2 CHARGE PUMP 3 COMP1 ON 15 1.234V VCC1 2A M6 M5 FILTER 11 M4 10A VCC1 2A 1.26V - + FAULT 13 M2 1.234V FILTER COMPARATOR FTRHI 1.6A TMRHI COMPARATOR + TMRHI - TMRLO COMPARATOR TMRLO - + FAULT COMPARATOR 0.3V 14 GND 1.234V FTR_CHARGE SYSTEM CONTROL FAULT + - DELAY ON COMPARATOR 12 TIMER CPO1 VCC1 OSC VCC1 CPO2 VCC2 VCC3 CPO3 1.234V VCC1 20A + - UVLO REF 0.25V TMRBUFFER 1.234V VCC1 FAULT + - COMP6 FAULTLO VCC1 50mV VCC1 6 CPO1 10A + - MG1 ON FAST COMP1 + FASTHI - FBCOMP1 FB1 10 1.234V + - POWER BAD GLITCH FILTER CHANNEL 1 CONTROL FPD GATELO COMPARATOR - GATELO + MF1 200A SLOW COMP1 SLOWHI 8 GATE 1 CUR_LIMIT CHANNEL ONE
+ -
+ -
0.25V
VCLAMP1 = VCC1 + 12V
VCC2 50mV VCC2 16
CPO2 10A + - SLOW COMP2 SLOWHI
CHANNEL TWO 18 GATE 2
+ -
CUR_LIMIT
MG2 FPD FAST COMP2 + FASTHI - FBCOMP2 CHANNEL 2 CONTROL FPD GATELO COMPARATOR - GATELO + MF2 200A
+ -
FB2 20 1.234V
+ - POWER BAD
GLITCH FILTER
0.25V
VCLAMP2 = VCC2 + 12V
VCC3 5 CHANNEL THREE (DUPLICATE OF CHANNEL TWO)
3 GATE 3
4230f
11
LTC4230
APPLICATIO S I FOR ATIO
HOT CIRCUIT INSERTION
When circuit boards are inserted into or removed from live backplanes, the supply bypass capacitors can draw huge transient currents from the backplane power bus as they charge. The transient currents can cause permanent damage to the connector pins as well as cause glitches on the system supply, causing other boards in the system to reset. The LTC4230 is designed to turn a printed circuit board's supply voltages on and off in a controlled manner, allowing the circuit board to be safely inserted or removed from a live backplane. The device provides a system reset signal to indicate when board supply voltage drops below a predetermined level, as well as a dual function fault monitor.
BACKPLANE PCB EDGE CONNECTOR CONNECTOR (MALE) (FEMALE) VCC LONG 3 1 RSENSE 2 4 Q1
ON/RESET
SHORT 15 ON
GND
LONG
Figure 1. Supply Voltage Monitor Block Diagram
12
U
OUTPUT VOLTAGE MONITOR The LTC4230 uses a 1.234V bandgap reference, precision voltage comparators and external resistor dividers to monitor the output supply voltages as shown in Figure 1. The operation of the supply monitor in normal mode is illustrated in Figure 2. RESET 1 pulls low during an undervoltage lockout condition. It remains low until the end of the soft-start cycle (second timing cycle). FB1 then assumes control of RESET 1 status. RESET 2 and RESET 3 also pull low during undervoltage lockout. However, FB2 controls RESET 2 and FB3 controls RESET 3 status immediately after clearing UVLO (Figure 2, Time Points 5 and 6). If the voltage at FBn drops below its reset threshold (1.234V), the FBCOMP comparator output pulls high. After passing through a glitch filter, RESETn changes state. If the voltage at FBn increases above its reset threshold, the FBCOMP comparator output changes state and RESETn pulls high.
+
GATEn R1 VOUT CLOAD LTC4230 VCCn SENSEn
W
U
U
+
LOGIC FBCOMPn
FBn R2
R3 10k
-
P TIMER 1.234V REFERENCE RESETn MRn TIMER 12 CTIMER GND 14
4230 F01
RESET
4230f
LTC4230
APPLICATIO S I FOR ATIO
OUT OF UVLO 1
VCCn, ON
UVLO (INTERNAL SIGNAL)
TIMER
20A PULL-UP
FIRST TIMING CYCLE
VOUT1
VOUT2, 3
RESET 1
RESET 2, RESET 3
GATEn GATEn < 0.25V
Figure 2. Supply Monitor Waveforms in Normal Mode
4230f
U
CHECK FOR FILTER LOW (< VREF) CHECK FOR FAULT HIGH (> VREF + 50mV) FAST COMPARATOR ARMED 234 5 SLOW COMPARATOR ARMED 6 1.234V 20A PULL-UP SECOND TIMING CYCLE (SOFT-START CYCLE) NORMAL MODE (VFB1 > 1.237V) (VFB2, VFB3 > 1.237V) 10A PULL-UP
4230 F02
W
U
U
13
LTC4230
APPLICATIO S I FOR ATIO
INTERNAL UNDERVOLTAGE LOCKOUT (UVLO) The LTC4230's power-on reset circuit initializes the startup condition and ensures the chip is in the proper state if the input supply voltages are too low. If any one of the input supply voltages falls below its corresponding UVLO lower threshold (e.g., VCC1 < 2.25V, VCC2 < 2.105V or VCC3 < 1.155V), the LTC4230 enters UVLO mode and all three GATEn pins are each pulled low by internal 200A current sinks. Since the LTC4230's UVLO circuits have hysteresis, the device restarts when all three supply voltages rise above their corresponding UVLO high threshold (e.g., VCC1 > 2.35V, VCC2 > 2.15V and VCC3 > 1.19V) and the ON pin goes high. In addition, users can utilize the ON comparator (COMP1) or the FAULT comparator (COMP6) to effectively program a higher undervoltage lockout level. If the FAULT comparator is used for this purpose, the system will wait for the input voltage to increase above the level set by the user before starting the second timing cycle. Also, if the input voltage drops below the set level in normal operating mode, the user must cycle the ON pin or VCC1 to restart the system. GLITCH FILTER FOR RESETn Each LTC4230 feedback comparator has a glitch filter to prevent RESETn from generating a system reset if there are transients on the FBn pin. The relationship between
250
0.3V
GLITCH FILTER TIME (s)
200
150 CTIMER 100
TIMER
50 M6 0
VREF 1.234V
-
NORMAL
0
20 40 60 80 100 120 140 160 180 200 FEEDBACK TRANSIENT (mV)
4211 F03
*ADDITIONAL DETAILS OMITTED FOR CLARITY
Figure 3. FB Comparator Glitch Filter Time vs Feedback Transient Voltage
Figure 4. LTC4230 System Timing Block Diagram
4230f
14
+
TA = 25C
-
U
glitch filter time and the feedback transient voltage is shown in Figure 3. SYSTEM TIMING System timing for the LTC4230 is generated in the equivalent circuit shown in Figure 4. If the LTC4230's internal timing circuit is off, an internal N-channel FET connects the TIMER pin to GND. If the timing circuit is enabled, an internal 20A current source is then connected to the TIMER pin to charge CTIMER at a rate given by Equation 1:
W
U
U
C TIMER Charge -Up Rate =
20A C TIMER
(1)
When the TIMER pin voltage reaches TMRHI's threshold of 1.234V, the TIMER pin is reset to GND. Equation 2 gives an expression for the timer period:
tTIMER = 1.234V *
C TIMER 20A
(2)
As a design aid, the LTC4230's timer period as a function of the CTIMER using standard values from 0.1F to 10F is shown in Table 1.
VCC1 20A
LTC4230*
tTIMER
TMRLO
LOGIC
+
TMRHI
4230 F04
LTC4230
APPLICATIO S I FOR ATIO
Table 1. tTIMER vs CTIMER
CTIMER 0.1F 0.22F 0.33F 0.47F 0.68F 0.82F 1F 2.2F 3.3F 4.7F 6.8F 8.2F 10F tTIMER 6.2ms 13.6ms 20.4ms 29ms 42ms 50.6ms 61.7ms 136ms 204ms 290ms 420ms 506ms 617ms
CHECK FOR FILTER LOW (< VREF) CHECK FOR FAULT HIGH (> VREF + 50mV) CHECK FOR GATEn < 0.2V 12 FAST COMPARATOR ARMED 345 6 SLOW COMPARATOR ARMED 7 8
ON SECOND TIMING CYCLE 20A PULL-UP
FIRST TIMING CYCLE 20A PULL-UP TIMER
GATEn 200A PULL-DOWN
10A PULL-UP
VOUTn
POWER GOOD (VFBn > 1.237V)
RESET 1
RESET 2, RESET 3
Figure 5. Normal Power-Up Sequence
4230f
U
Ensuring a proper start-up sequence is also dependent on selecting the most appropriate value for CTIMER for the application. Long timing periods affect overall system start-up times. A timing period set too short and the system may never start up. A good starting point is to set CTIMER = 1F and then adjust its value accordingly for the application. OPERATING SEQUENCE Power-Up, Start-Up Check and Plug-In Timing Cycle The sequence of operations for the LTC4230 is illustrated in the timing diagram of Figure 5. When a PC board is first inserted into a live backplane, the LTC4230 first performs
IF ON IS LOW AND VFBn < 1.234V, RESET 1, RESET 2 AND RESET 3 PULL LOW, RESPECTIVELY 9 NORMAL MODE 200A PULL-DOWN POWER BAD (VFBn < 1.234V)
4230 F05
W
U
U
15
LTC4230
APPLICATIO S I FOR ATIO
a start-up check to make sure the supply voltage is above its 2.3V UVLO threshold (see Time Point 1). If the input supply voltage is valid, the gate of the external pass transistor is pulled to ground by the internal 200A current source connected at the GATEn pin. The TIMER pin is held low by an internal N-channel pull-down transistor (see M6, LTC4230 Block Diagram) and the FILTER pin voltage is pulled to ground by an internal 10A current source. Once VCCn and ON (the ON pin is >1.314V) are valid, the LTC4230 checks to make sure that GATEn is OFF (VGATEn < 0.25V) at Time Point 2. An internal timing circuit is enabled and the TIMER pin voltage ramps up at the rate described by Equation 1. At Time Point 3 (the timing period programmed by CTIMER), the TIMER pin voltage equals VTMR (1.234V). Next, the TIMER pin voltage ramps down to Time Point 4 where the LTC4230 performs two checks: (1) FILTER pin voltage is low (VFILTER < 1.19V) and (2) FAULT pin voltage is high (VFAULT > 1.284V). If both conditions are met, the LTC4230 begins a second timing (soft-start) cycle. Second Timing (Soft-Start) Cycle At the beginning of the second timing cycle (Time Point 5), the LTC4230's FAST COMPn is armed and an internal 10A current source working with an internal charge pump provides the gate drive to the external pass transistor. An expression for the GATEn voltage slew rate is given by Equation 3:
VGATEn Slew Rate,
dVGATEn 10A = dt C GATEn
where CGATEn = Power MOSFET gate input capacitance (CISS) for Channel n. For example, a Si4410DY (a 30V N-channel power MOSFET) exhibits an approximate CGATE of 3300pF at VGS = 10V. The LTC4230's GATEn voltage rate-of-change (slew rate) for this example would be:
VGATEn Slew Rate,
dVGATEn 10A V = = 3.03 dt 3300pF ms
The inrush current being delivered to the load while the GATEn is ramping is dependent on CLOADn and CGATEn.
16
U
Equation 4 gives an expression for the inrush current during the second timing cycle:
IINRUSH = dVGATEn C * C LOADn = 10A * LOADn dt C GATEn
W
U
U
(4)
For example, if CGATEn = 3300pF and CLOADn = 2000F, the inrush current charging CLOADn is:
IINRUSH = 10A *
2000F = 6.06A 0.0033F
(5)
At Time Point 7, the output voltage trips FBCOMPn's threshold, signaling an output voltage "power good" condition. RESET 2 and RESET 3 pull high. At Time Point 8, RESET 1 asserts high, SLOW COMP is armed and the LTC4230 enters a fault monitor mode. SOFT-START WITH CURRENT LIMITING During the second timing cycle, the inrush current is described by Equation 4. Note that there is a one-to-one correspondence in the inrush current to CLOADn. If the inrush current is large enough to cause a voltage drop greater than 50mV across the sense resistor, an internal servo loop controls the operation of the 10A current source at the GATEn pin to regulate the load current to:
ILIMIT (SOFTSTART)n = 50mV RSENSEn
(6)
(3)
For example, the inrush current is limited to 5A when RSENSEn = 0.01. In this fashion, the inrush current is controlled and CLOADn is charged up slowly during the soft-start cycle. The timing diagram in Figure 6 illustrates the operation of the LTC4230 in a normal power-up sequence with limited inrush current as described by Equation 6. At Time Point 5, the GATE pin voltage begins to ramp indicating that the power MOSFET is beginning to charge CLOADn. At Time Point 5, the inrush current causes a 50mV voltage drop across RSENSEn and an internal servo loop engages, limiting the inrush current to a fixed level. At Time Point 6, the GATEn pin voltage continues to ramp as CLOADn charges until VOUTn reaches its final value. The charging current
4230f
LTC4230
APPLICATIO S I FOR ATIO
reduces, and the internal servo loop disengages. At the end of the soft-start cycle (Time Point 8), all RESETn are high and all SLOW COMPn are armed. Power-Off Cycle As shown at Time Point 9, an external hard reset is initiated by pulling the ON pin low (VON < 1.234V). All GATEn pin voltages are ramped to ground by the internal 200A current sources, discharging CGATEn and turning off the pass transistors. As CLOADn discharges, the output voltage crosses FBCOMPn's threshold, signaling a "power bad" condition at Time Point 10. RESETn then asserts low.
CHECK FOR FILTER LOW (< VREF) CHECK FOR FAULT HIGH (> VREF + 50mV) CHECK FOR GATEn < 0.25V 12 FAST COMPARATOR ARMED 6 7 SLOW COMPARATOR ARMED 8
34 5
ON SECOND TIMING CYCLE 20A PULL-UP
FIRST TIMING CYCLE 20A PULL-UP TIMER
10A PULL-UP VOUTn GATEn VOUTn 200A PULL-DOWN POWER GOOD (VFBn > 1.237V) 200A PULL-DOWN
LOAD CURRENT IS REGULATING AT 50mV/RSENSEn
ILOADn
RESET 1
RESET 2, RESET 3
Figure 6. Normal Power-Up Sequence (with Current Limiting in Second Timing Cycle)
4230f
U
FREQUENCY COMPENSATION AT SOFT-START If the external gate input capacitance (CISS) is greater than 600pF, no external gate capacitor is required at GATEn to stabilize the internal current-limiting loop during softstart. Otherwise, connect an external gate capacitor between the GATEn and GND pins to increase the total gate capacitance above 600pF. The servo loop that controls the external MOSFET during current limiting has a unity-gain frequency of about 105kHz and phase margin of 80 for external MOSFET gate input capacitances to 2.5nF.
IF ON IS LOW AND VFBn < 1.234V, RESET 1, RESET 2 and RESET 3 PULL LOW, RESPECTIVELY 9 10 NORMAL MODE GATEn POWER BAD (VFBn < 1.234V)
4230 F06
W
U
U
17
LTC4230
APPLICATIO S I FOR ATIO
USING AN EXTERNAL GATE CAPACITOR
The LTC4230 automatically limits the inrush current in one of two ways: by controlling the GATEn pin voltage slew rate or by actively limiting the inrush current. The LTC4230 uses GATEn voltage slew rate limiting when CLOADn is small and/or the inrush current limit is set high. If GATEn voltage slew rate control is preferred with large CLOADn, an external capacitor (CGX) can be used from GATEn to ground, as shown in Figure 7. According to Equation 3, adding CGX slows the GATEn voltage slew rate at the expense of slower system turn-on and turn-off time. Should this technique be used, values for CGX less than 150nF are recommended.
VIN 5V RSENSE 1 0.007 2 3 4 M1 Si4410DY CGX* R1 36k VCCn SENSEn LTC4230** GATEn FBn R2 15k
4230 F07
+
CLOAD
*VALUES 150nF SUGGESTED **ADDITIONAL DETAILS OMITTED FOR CLARITY
VGATE SLEW RATE CONTROL 10A dVGATEn = dt CGATE + CGX
(
)
Figure 7. Using an External Capacitor at GATE for GATE Voltage Slew Rate Control and Large CLOAD
An external gate capacitor may also be useful to decrease or eliminate current spikes through the MOSFET when power is first applied. At power-up, the instantaneous input voltage step attempts to pull the MOSFET gate up through the MOSFET's drain-to-gate capacitance. If the MOSFET's CISS is small, the gate can be pulled up high enough to turn on the MOSFET, thereby allowing a current spike to the output. This event occurs during the time that the LTC4230 is coming out of UVLO and getting its intelligence to hold the GATE pin low. An external capacitor attenuates the voltage to which the GATE is pulled up and eliminates the current spike. The value required is dependent on the MOSFET capacitance specifications. In typical applications, this capacitor is not required.
18
U
ELECTRONIC CIRCUIT BREAKER The LTC4230 features an electronic circuit breaker function. It disconnects loads from power supplies when shorts or excessive load current conditions occur on any of the supplies and generates a FAULT signal. If a circuit breaker trips, its GATEn pin is immediately pulled to ground, the external N-channel MOSFET is quickly turned OFF and FAULT is latched low. The circuit breaker trips whenever the voltage across the sense resistor exceeds two different levels, each level set by the LTC4230's SLOW COMPn and FAST COMPn (see Block Diagram). The SLOW COMPn trips the circuit breaker if the voltage across the SENSEn resistor (VCCn - VSENSEn = VCB) is greater than 50mV for 10s. There may be applications where this comparator's response time is not long enough, for example, because of excessive supply voltage noise. To adjust the response time of the SLOW COMPn, a capacitor is used at the LTC4230's FILTER pin (see section on Adjusting SLOW COMPn's Response Time). The FAST COMPn trips the circuit breaker to protect against fast load overcurrents if the transient voltage across the sense resistor is greater than 150mV for 500ns. The response time of the LTC4230's FAST COMPn is fixed. The timing diagram of Figure 6 illustrates when the LTC4230's electronic circuit breaker is armed. After the first timing cycle, the LTC4230's FAST COMPn is armed at Time Point 5. Arming FAST COMPn at Time Point 5 ensures that the system is protected against a shortcircuit condition during the second timing cycle after CLOADn has been fully charged. At Time Point 8, SLOW COMPn is armed when the internal control loop is disengaged. The timing diagrams in Figures 8 and 9 illustrate the operation of the LTC4230 when the load current conditions exceed the thresholds of the FAST COMPn (VCB(FAST) > 150mV) and SLOW COMPn (VCB(SLOW) > 50mV), respectively.
VOUT 5V 5A
4230f
W
U
U
LTC4230
APPLICATIO S I FOR ATIO
RESETTING THE ELECTRONIC CIRCUIT BREAKER Once the LTC4230's circuit breaker is tripped, FAULT is asserted low and the GATEn pin is pulled to ground. The LTC4230 remains latched OFF in this fault state until the external fault is cleared. To clear the internal fault detect
CHECK FOR FILTER LOW (< VREF) CHECK FOR FAULT HIGH (> VREF + 50mV) CHECK FOR GATEn < 0.25V 12 FAST COMPARATOR ARMED 34 5 SLOW COMPARATOR ARMED CIRCUIT BREAKER TRIPS, ALL GATEn PINS PULL LOW IMMEDIATELY 6 7 CHECK FOR TIMER < 0.3V 8 9
ON
20A PULL-UP TIMER
20A PULL-UP
GATEn GATEn VOUTn
VOUTn
FAULT
LOAD CURRENT < 50mV/RSENSEn IOUTn
FILTER
Figure 8. Output Short Circuit Causes Fast Comparator to Trip the Circuit Breaker
U
circuitry and to restart the LTC4230, its ON pin must be driven low (VON < 1.234V) for at least 30s, after which time FAULT goes high. Toggling the ON pin from low to high (VON > 1.314V) initiates a restart sequence in the LTC4230. The timing diagram in Figure 10 illustrates a
1.6A PULL-DOWN LOAD CURRENT > 150mV/RSENSEn
4230 F08
W
U
U
4230f
19
LTC4230
APPLICATIO S I FOR ATIO
CHECK FOR FILTER LOW (< VREF) CHECK FOR FAULT HIGH (> VREF + 50mV) CHECK FOR GATEn < 0.25V 12 FAST COMPARATOR ARMED 345 SLOW COMPARATOR ARMED CIRCUIT BREAKER TRIPS, ALL GATEn PINS PULL LOW IMMEDIATELY 6 7 CHECK FOR TIMER < 0.3V 8 9
ON
20A PULL-UP TIMER
20A PULL-UP
GATEn GATEn VOUTn
VOUTn
FAULT
IOUTn
LOAD CURRENT < 50mV/RSENSEn
FILTER
2A PULL-UP
Figure 9. Output Short-Circuit Causes Slow Comparator to Trip Circuit Breaker
20
U
1.6A PULL-DOWN 150mV/RSENSEn > LOAD CURRENT > 50mV/RSENSEn 1.26V 10A PULL-DOWN
4230 F09
W
U
U
4230f
CHECK FOR GATEn < 0.25V CHECK FOR TIMER < 0.3V 9 10 6 7 8
FAST COMPARATOR ARMED SLOW COMPARATOR ARMED ONCE VFILTER > 1.26V, CIRCUIT BREAKER TRIPS, ALL GATEn PINS PULL LOW IMMEDIATELY
12
345
ON
APPLICATIO S I FOR ATIO U
4230 F10
FIRST TIMING CYCLE 20A PULL-UP 1.6A PULL-DOWN
SECOND TIMING CYCLE NORMAL MODE DISCHARGING MODE
TIMER GATEn
GATEn VOUTn VOUTn LOAD CURRENT < 150mV/RSENSEn
LOAD CURRENT IS REGULATING AT 50mV/RSENSEn
ILOADn VFILTER > 1.26V 2A PULL-UP 10A PULL-DOWN
FILTER
FAULT
Figure 10. Power-Up into Dead Short in Overcurrent Condition
U
LTC4230
20A PULL-UP
W
U
CHECK FOR FILTER LOW (< VREF) CHECK FOR FAULT HIGH (> VREF + 50mV)
21
4230f
LTC4230
APPLICATIO S I FOR ATIO
start-up sequence where the LTC4230 is powered up into a load overcurrent condition. Note that the circuit breaker trips at Time Point 8 and is reset at Time Point 10. ADJUSTING SLOW COMPn'S RESPONSE TIME The response time of SLOW COMPn is adjusted using a capacitor connected from the LTC4230's FILTER pin to ground. If this pin is left unused, SLOW COMPn's delay defaults to 10s. During normal operation, the FILTER output pin is held low as an internal 10A pull-down current source is connected to this pin by transistor M4. This pull-down current source is turned off when an overcurrent load condition is detected by SLOW COMPn. During an overcurrent condition, the internal 2A pull-up current source is connected to the FILTER pin by transistor M5, thereby charging CFILTER. As the charge on the capacitor accumulates, the voltage across CFILTER increases. Once the FILTER pin voltage increases to 1.26V, the electronic circuit breaker trips and the LTC4230's GATEn pins are switched quickly to ground by transistor MFn (refer to the Block Diagram). After the circuit breaker is tripped, M5 is turned off, M4 is turned on and the 10A pull-down current then holds the FILTER pin voltage low. SLOW COMPn's response time from an overcurrent fault condition to when the circuit breaker trips (GATEn OFF) is given by Equation 7:
tSLOWCOMPn = 1.26V *
C FILTER + 10s 2A
For example, if CFILTER = 1000pF, SLOW COMPn's response time = 640s. As a design aid, SLOW COMPn's delay time (tSLOW COMP) versus CFILTER for standard values of CFILTER from 100pF to 1000pF is illustrated in Table 2.
Table 2. tSLOWCOMPn vs CFILTER
CFILTER 100pF 220pF 330pF 470pF 680pF 820pF 1000pF tSLOWCOMPn 73s 149s 218s 306s 438s 527s 640s
22
U
SENSE RESISTOR CONSIDERATIONS The fault current level at which the LTC4230's internal electronic circuit breakers trip is determined by a sense resistor connected between the LTC4230's VCCn and SENSEn pins and two separate trip points. The first trip point is set by the SLOW COMPn's threshold, VCB(SLOW) = 50mV, and the trip occurs if a load current fault condition exist for more than 10s. The current level at which the electronic circuit breaker trips is given by Equation 8: ITRIP(SLOW)n = VCB(SLOW)n 50mV = RSENSEn RSENSEn (8) The second trip point is set by the FAST COMPn's threshold, VCB(FAST) = 150mV, and occurs during fast load current transients that exist for 500ns or longer. The current level at which the circuit breaker trips in this case is given by Equation 9: ITRIP(FAST )n = VCB(FAST )n 150mV = RSENSEn RSENSEn (9) As a design aid, the currents at which electronic circuit breaker trips for common values for RSENSE are shown in Table 3.
Table 3. ITRIP(SLOW) and ITRIP(FAST) vs RSENSE
RSENSE 0.005 0.006 0.007 0.008 0.009 0.01 ITRIP(SLOW) 10A 8.3A 7.1A 6.3A 5.6A 5A ITRIP(FAST) 30A 25A 21A 19A 17A 15A
W
U
U
(7)
For proper circuit breaker operation, Kelvin-sense PCB connections between the sense resistor and the LTC4230's VCCn and SENSEn pins are strongly recommended. The drawing in Figure 11 illustrates the correct way of making connections between the LTC4230 and the sense resistor. PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation.
4230f
LTC4230
APPLICATIO S I FOR ATIO
The power rating of the sense resistor should accommodate steady-state fault current levels so that the component is not damaged before the circuit breaker trips. Table 4 in the Appendix lists suggested sense resistors that can be used with the LTC4230's circuit breaker.
CURRENT FLOW TO LOAD IRC-TT SENSE RESISTOR LR251201R010F OR EQUIVALENT 0.01, 1%, 1W CURRENT FLOW TO LOAD
TRACK WIDTH W: 0.03" PER AMP ON 1 OZ COPPER
W
TO VCCn
TO SENSEn
Figure 11. Making PCB Connections to the Sense Resistor
CALCULATING CIRCUIT BREAKER TRIP CURRENT For a selected RSENSE value, the nominal load current that trips the circuit breaker is given by Equation 10:
ITRIP(NOM) =
VCB(NOM) RSENSE(NOM)
=
50mV RSENSE(NOM)
The minimum load current that trips the circuit breaker is given by Equation 11.
ITRIP(MIN) = VCB(MIN) RSENSE(MAX) = 40mV RSENSE(MAX)
where
R RSENSE(MAX) = RSENSE(NOM) * 1 + TOL 100
The maximum load current that trips the circuit breaker is given in Equation 12.
ITRIP(MAX) = VCB(MAX) 60mV = RSENSE(MIN) RSENSE(MIN)
where
RSENSE(MIN)
R = RSENSE(NOM) * 1 - TOL 100
U
For example: If a sense resistor with 7m 5% RTOL is used for current limiting, the nominal trip current ITRIP(NOM) = 7.1A. From Equations 11 and 12, ITRIP(MIN) = 5.4A and ITRIP(MAX) = 9A respectively. For proper operation and to avoid the circuit breaker tripping unnecessarily, the minimum trip current (ITRIP(MIN)) must exceed the circuit's maximum operating load current. For reliability purposes, the operation at the maximum trip current (ITRIP(MAX)) must be evaluated carefully. If necessary, two resistors with the same RTOL can be connected in parallel to yield an RSENSE(NOM) value that fits the circuit requirements.
ILOAD(MAX) VCCn 5V 3 1 RSENSE 2 4 VOUTn
4230 F11
W
U
U
LTC4230*
VCCn VCBn
SENSEn
+ - +
SLOW COMPn
-
VCB(MAX) = 60mV VCB(NOM) = 50mV VCB(MIN) = 40mV
4230 F12
(10)
*ADDITIONAL DETAILS OMITTED FOR CLARITY
Figure 12. Circuit Breaker Equivalent Circuit for Calculating RSENSE
(11)
POWER MOSFET SELECTION CRITERIA To start the power MOSFET selection process, choose the maximum drain-to-source voltage, VDS(MAX), and the maximum drain current, ID(MAX) of the MOSFET. The VDS(MAX) rating must exceed the maximum input supply voltage (including surges, spikes, ringing, etc.) and the ID(MAX) rating must exceed the maximum short-circuit current in the system during a fault condition. In addition, consider three other key parameters: 1) the required gatesource (VGS) voltage drive, 2) the voltage drop across the drain-to-source ON resistance, RDS(ON) and 3) the maximum junction temperature rating of the MOSFET. Power MOSFETs are classified into two categories: standard MOSFETs (RDS(ON) specified at VGS = 10V) and logiclevel MOSFETs (RDS(ON) specified at VGS = 5V). The absolute
4230f
(12)
23
LTC4230
APPLICATIO S I FOR ATIO
maximum rating for VGS is typically 20V for standard MOSFETs. However, the VGS maximum rating for logiclevel MOSFETs ranges from 8V to 20V depending upon the manufacturer and the specific part number. The LTC4230's gate overdrive as a function of VCC is illustrated in the Typical Performance curves. Logic-level MOSFETs are recommended for low supply voltage applications and standard MOSFETs can be used for applications where supply voltage is greater than 4.75V. Note that in some applications, the gate of the external MOSFET can discharge faster than the output voltage when the circuit breaker is tripped. This causes a negative VGS voltage on the external MOSFET. Usually, the selected external MOSFET should have a VGS(MAX) rating that is higher than the operating input supply voltage to ensure that the external MOSFET is not destroyed by a negative VGS voltage. In addition, the VGS(MAX) rating of the MOSFET must be higher than the gate overdrive voltage. Lower VGS(MAX) rating MOSFETs can be used with the LTC4230 if the GATEn overdrive is clamped to a lower voltage. The circuit in Figure 13 illustrates the use of zener diodes to clamp the LTC4230's GATEn overdrive signal if lower voltage MOSFETs are used. The RDS(ON) of the external pass transistor should be low to make its drain-source voltage (VDS) a small percentage of VCC. At a VCC = 2.5V, VDS + VRSENSE = 0.1V yields 4% error at the output voltage. This restricts the choice of MOSFETs to very low RDS(ON). At higher VCC voltages, the VDS requirement can be relaxed in which case MOSFET package dissipation (PD and TJ) may limit the value of RDS(ON). Table 5 lists some power MOSFETs that can be used with the LTC4230. Power MOSFET junction temperature is dependent on four parameters: current delivered to the load, ILOAD, RDS(ON), junction-to-ambient thermal resistance, JA, and the maximum ambient temperature to which the circuit will be exposed, TA(MAX). For reliable circuit operation, the maximum junction temperature (TJ(MAX)) for a power MOSFET should not exceed the manufacturer's recommended value.
24
U
This includes normal mode operation, start-up, currentlimit and autoretry mode in a fault condition. For a given set of conditions, the junction temperature of a power MOSFET is given by Equation 13: MOSFET Junction Temperature, TJ(MAX) (TA(MAX) + JA * PD) where PD = (ILOAD)2 * RDS(ON) PCB layout techniques for optimal thermal management of power MOSFET power dissipation help to keep device JA as low as possible. See the section on PCB Layout Considerations for more information.
RSENSE Q1 VCC D1* D2* VOUT
W
U
U
(13)
RG 200 GATE
4230 F13
*USER SELECTED VOLTAGE CLAMP (A LOW BIAS CURRENT ZENER DIODE IS RECOMMENDED) 1N4688 (5V) 1N4692 (7V): LOGIC-LEVEL MOSFET 1N4695 (9V) 1N4702 (15V): STANDARD-LEVEL MOSFET
Figure 13. Optional Gate Clamp for Lower VGS(MAX) MOSFETs
USING STAGGERED PIN CONNECTORS The LTC4230 can be used on either a printed circuit board or on the backplane side of the connector, and examples for both are shown in Figure 14. Printed circuit board edge connectors with staggered pins are recommended as the insertion and removal of circuit boards do sequence the pin connections. Supply voltage and ground connections on the printed circuit board should be wired to the edge connector's long pins or blades. Control and status signals (like RESETn, FAULT and ON) passing through the card's edge connector should be wired to short length pins or blades.
4230f
LTC4230
APPLICATIO S I FOR ATIO
PCB CONNECTION SENSE
There are a number of ways to use the LTC4230's ON pin to detect whether the printed circuit board has been fully seated in the backplane before the LTC4230 commences a start-up cycle. The first example is shown in the schematic on the front page of this data sheet. In this case, the LTC4230 is mounted on the PCB and a 10k resistive divider is connected to the ON pin. On the edge connector, R1 is wired to a short pin. Until the connectors are fully mated, the ON pin is held low, keeping the LTC4230 in an OFF state. Once the connectors are mated, the resistive divider is connected to VCC1, VON > 1.314V and the LTC4230 begins a start-up cycle.
BACKPLANE PCB EDGE CONNECTOR CONNECTOR (MALE) (FEMALE) VCC LONG Z1** SHORT SHORT
VIN 5V R1 10 C1 0.1F 3 R6 10k RESETn ON VCCn SENSEn LTC4230* 14 GATEn GND TIMER 12 CTIMER 1F FBn
RESET
LONG Z1: SMAJ10 *ADDITIONAL DETAILS OMITTED FOR CLARITY **OPTIONAL
(14a) Hot Swap Controller On Daughter Board
BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) LONG
VCC 5V Z1** RX 10 CX 0.1F PCB CONNECTION SENSE
R5 10k
R4 10k 15 Q2 14
VCCn ON
GND TIMER 12
Z1: SMAJ10 *ADDITIONAL DETAILS OMITTED FOR CLARITY **OPTIONAL
(14b) Hot Swap Controller on Backplane Figure 14. Staggered Pin Connections
4230f
U
In Figure 14a, an LTC4230 is illustrated in a basic configuration on a PCB daughter card. The ON pin is connected directly to VCC on the backplane once the card is seated into the backplane. R2 is provided to bleed off any potential static charge which might exist on the backplane, the connector or during card installation. A third example is shown in Figure 14b where the LTC4230 is mounted on the backplane. In this example, a 2N2222 transistor and a pair of resistors (R4, R5) form the PCB connection sense circuit. With the card out of the chassis, Q2's base is biased to VCC through R5, biasing Q2 on and driving the LTC4230's ON pin low. The base of Q2 is also wired to a socket on the backplane connector. When a card is firmly seated into the backplane, the base of Q2 is then grounded through a short pin connection on the card. Q2 is biased off, the LTC4230's ON pin is pulled-up to VCC and a start-up cycle begins.
RSENSE 1 0.007 2 4 Q1 Si4410DY VOUT 5V 5A
W
U
U
+
COUT R4 36k R5 15k
4230 F14a
RESET 15 R2 10k
RSENSE 1 0.007 2 3 4
Q1 Si4410DY
+
LONG COUT R1 36k R3 10k
VOUT 5V 5A
SENSEn
GATEn LTC4230* RESETn FBn
SHORT SHORT SHORT
RESET R2 100k
4230 F14b
CTIMER 1F
R7 15k
25
LTC4230
APPLICATIO S I FOR ATIO
In the previous three examples, the connection sense was hard wired with no processor (low) interrupt capability. As illustrated in Figure 15, the addition of an inexpensive logic-level discrete MOSFET and a couple of resistors offers processor interrupt control to the connection sense. R4 keeps the gate of M2 at VCC until the card is firmly mated to the backplane. A logic low for the ON/OFF signal turns M2 off, allows the ON pin to pull high and turns on the LTC4230. A more elaborate connection sense scheme is shown in Figure 16. The bases of Q1 and Q2 are wired to short pins located on opposite ends of the edge connector because the installation/removal of printed circuit cards generally
BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) VCC 5V LONG RX 10 CX 100nF
Z1
SHORT SHORT
R1 10k
ON/OFF
GND
LONG
PCB CONNECTION SENSE *ADDITIONAL DETAILS OMITTED FOR CLARITY
Z1: SMAJ10 M2: 2N7002LT1
Figure 15. Connection Sense with ON/OFF Control
BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE)
LAST BLADE OR PIN ON CONNECTOR SHORT PCB CONNECTION SENSE RSENSE 1 0.007 2 3 R1 10k R2 10k R3 10k VCCn 15 R8 10k Q1 Q2 TIMER 12 M1 CTIMER 1F
4230 F16
VCC
LONG RX 10 CX 0.1F
Z1
ON/RESET GND
SHORT LONG SHORT
LAST BLADE OR PIN ON CONNECTOR
Figure 16. Connection Sense for Rocking the Daughter Board Back and Forth
4230f
26
U
requires rocking the card back and forth. When VCC makes connection, the bases of transistors Q1 and Q2 are pulled high, biasing them on. When both are on, the LTC4230's ON pin is held low, keeping the LTC4230 off. When the short base connector pins of Q1 and Q2 finally mate to the backplane, their bases are grounded, biasing the transistors off. The ON pin is then pulled high by R3 enabling the LTC4230 and a power-up cycle begins. A software-initiated power-down cycle can be started by momentarily driving transistor M1 with a logic high signal. This in turn will drive the LTC4230's ON pin low. If the ON pin is held low for more than 8s, the LTC4230's GATEn pin is switched to ground.
RSENSE 1 0.007 2 3 4 M1 Si4410DY
W
U
U
+
CLOAD R5 36k R6 15k RESETn R7 10k P LOGIC RESET
VOUT 5V 5A
VCCn R4 10k 15 M2
SENSEn
GATEn FBn
ON
LTC4230*
R2 10k
TIMER 12 CTIMER 1F
GND 14
4230 F15
M2 Si4410DY
4
+
CLOAD R4 36k R5 15k RESETn GND 14 R7 10k P LOGIC RESET
VOUT 5V 5A
SENSEn
GATEn FBn
ON
LTC4230*
Z1: SMAJ10 M1: 2N7002LT1 Q1, Q2: MMBT3904LT1
*ADDITIONAL DETAILS OMITTED FOR CLARITY
LTC4230
APPLICATIO S I FOR ATIO
HIGH SUPPLY VOLTAGE OPERATION CONSIDERATIONS
The LTC4230 can be used with supply voltages ranging from 1.7V to 16.5V. At high input supply voltages, the internal charge pump produces a minimum gate drive voltage of 7V for VCC > 15V. This minimum voltage drive is derived by an internal zener diode clamp circuit, as shown in Figure 17. During PC board insertion or removal, sufficient transient current may flow through this zener diode. To limit the amount of current during transient events, an optional small resistor between the LTC4230's GATEn pin and the gate of the external MOSFET can be used, as shown in Figure 17. A secondary benefit of this component is to minimize the possibility of high frequency parasitic oscillations in the power MOSFET.
RSENSE1 0.007 Z1 BACKPLANE CONNECTOR (FEMALE) VCC1 3.3V VCC2 2.5V VCC3 1.8V PCB EDGE CONNECTOR (MALE) LONG Z2 LONG LONG RX3 10 CX3 100nF RX1 10 CX1 100nF
M1 IRF7413
RX2 10 CX2 100nF RSENSE3 0.007 M3 IRF7413
Z3
FAULT GND
SHORT LONG
RAUTO 1M 6 VCC1 14 15 GND ON RESET 3 13 CAUTO 0.1F FAULT LTC4230 2 R10 11k R11 12k RESET 2 RESET 1 19 9 R12 18k R13 12k R6 10k R5 10k 7 SENSE 1 8 GATE 1 16 VCC2 17 SENSE 2 18 GATE 2 5 VCC3 4 SENSE 3 3 GATE 3 FB3 1 R8 5.1k R9 12k R7 10k
* SYSTEM ON TIME: 6.2ms **CIRCUIT BREAKER RESPONSE TIME: 19.5s Z1, Z2, Z3: Z1: SMAJ10 NOTE: M1 MOUNTED TO 300mm COPPER AREA WITHOUT CAUTO YIELDS 8% AND M1 CASE = 65C WITH CAUTO = 0.1F YIELDS 4% and M1 CASE = 45C CTIMER* 0.1F
Figure 18. Autoretry Application
4230f
U
VCC > 15V 1 RSENSE 2 3 4 RZX VCCn LTC4230* VZ (TYP) = 26V SENSEn 10A CHARGE PUMP VOUT R1 FBn R2 200A 10A LOGIC *ADDITIONAL DETAILS OMITTED FOR CLARITY
4230 F17
W
U
U
Figure 17. Using an External Resistor to Limit Zener Current in High VCC Applications
+
VOUT1 3.3V 5A COUT1
RSENSE2 0.007
M2 IRF7413
+
VOUT2 2.5V 5A COUT2
+
VOUT3 1.8V 5A COUT3
P OR SYSTEM LOGIC MASTER RESET
3-INPUT NOR GATE
FB2
20
TIMER 12
FILTER CFILTER** 15pF 11
FB1
10
4230 F18
27
LTC4230
APPLICATIO S I FOR ATIO
AUTORETRY AFTER A FAULT
To configure the LTC4230 to automatically retry after a fault condition, the FAULT (which has an internal 2A pullup current source) and ON pins can be connected together, as shown in Figure 18. In this case, the autoretry circuitry will attempt to restart the LTC4230 with an 7% duty cycle, as shown in the timing diagram of Figure 19. To prevent overheating the external MOSFET and other components during the autoretry sequence, adding a capacitor (CAUTO) to the circuit introduces a delay at the ON pin that adjusts the autoretry duty cycle. Equation 14 gives the autoretry duty cycle, modified by the external time constant CAUTO:
Autoretry Duty Cycle = tTIMER * 100% (14) tOFF + 14.5 * tTIMER
where tTIMER = LTC4230 system time constant (see TIMER function) and
CHECK FOR FILTER LOW (< VREF) CHECK FOR FAULT HIGH (> VREF + 50mV) CHECK FOR GATEn < 0.25V 12 FAST COMPARATOR ARMED 34 5 6 SLOW COMPARATOR ARMED 7 ONCE VFILTER > 1.26V, CIRCUIT BREAKER TRIPS, ALL GATEn PINS PULL LOW IMMEDIATELY 8 CHECK FOR TIMER < 0.3V 9
ON/ FAULT FIRST TIMING CYCLE 20A PULL-UP TIMER GATEn SECOND TIMING CYCLE 20A PULL-UP NORMAL MODE DISCHARGING MODE 1.6A PULL-DOWN
GATEn VOUTn VSENSEn = 50mV ILOADn REGULATED LOAD CURRENT
2A PULL-UP FILTER
Figure 19. Autoretry Timing
4230f
28
U
tOFF = C AUTO * 1.314V 2A
W
U
U
For the values shown, the external delay equals 65.7ms and the autoretry duty cycle drops from 7% to 4%. To increase the RC delay, the user may either increase CAUTO or RAUTO. OVERVOLTAGE TRANSIENT PROTECTION Good engineering practice calls for bypassing the supply rail of any analog circuit. Bypass capacitors are often placed at the supply connection of every active device, in addition to one or more large value bulk bypass capacitors per supply rail. If power is connected abruptly, the large bypass capacitors slow the rate of rise of the supply voltage and heavily damp any parasitic resonance of lead or PC track inductance working against the supply bypass capacitors.
VOUTn LOAD CURRENT < 150mV/RSENSEn
VFILTER > 1.26V VREF 10A PULL-DOWN
4230 F19
LTC4230
APPLICATIO S I FOR ATIO
The opposite is true for LTC4230 Hot Swap circuits mounted on plug-in cards. In most cases, there is no supply bypass capacitor present on the powered supply voltage side of the MOSFET switch. An abrupt connection, produced by inserting the board into a backplane connector, results in a fast rising edge applied on the supply line of the LTC4230. Since there is no bulk capacitance to damp the parasitic track inductance, supply voltage transients excite parasitic resonant circuits formed by the power MOSFET capacitance and the combined parasitic inductance from the wiring harness, the backplane and the circuit board traces. These ringing transients appear as a fast edge on the input supply line, exhibiting a peak overshoot to 2.5 times the steady-state value. This peak is followed by a damped sinusoidal response whose duration and period are dependent on the resonant circuit parameters. Since the absolute maximum supply voltage of the LTC4230 is 17V, transient protection against VCC > 16.8V supply voltage spikes and ringing is highly recommended. In these applications, there are two methods for eliminating these supply voltage transients: using zener diodes to clip the transient to a safe level and snubber networks. Snubber networks are series RC networks whose time constants are experimentally determined based on the board's parasitic resonance circuits. As a starting point, the capacitors in these networks are chosen to be 10x to 100x the power MOSFET's COSS under bias. The series resistor is a value determined experimentally and ranges from 1 to 50, depending on the parasitic resonance circuit. Note that in all LTC4230 circuit schematics,
RSENSE 1 0.007 2 VIN 3 4 Qn Si4410DY
+
CLOADn R1
VCCn 10 SMAJ10 0.1F GND 14
SENSEn
GATEn FBn
LTC4230* RESETn ON CTIMER 15
R2
10 11
TIMER 12
RESET ON
*ADDITIONAL DETAILS OMITTED FOR CLARITY
4230 F20
Figure 20. Placing Transient Protection Devices Close to the LTC4230
U
TransZorb(R) diodes and snubber networks have been added to each 3.3V and 5V supply rail. These protection networks should be mounted very close to the LTC4230's supply voltage using short lead lengths to minimize lead inductance. This is shown schematically in Figure 20, and a recommended layout of the transient protection devices around the LTC4230 is shown in Figure 21. ADDITIONAL SUPPLY OVERVOLTAGE DETECTION/PROTECTION In addition to using external protection devices around the LTC4230 for large scale transient protection, low power zener diodes can be used with the LTC4230's FILTER pin to act as a supply overvoltage detection/protection circuit on either the high side (input) or low side (output) of the external pass transistor. Recall that internal control circuitry keeps the LTC4230 GATEn voltage from ramping up if VFILTER > 1.26V, or when an external fault condition (VFAULT < 1.234V) causes FAULT to be asserted low. High Side (Input) Overvoltage Protection As shown in Figure 22, a low power zener diode can be used to sense an overvoltage condition on the input (high) side of the main 5V supply. In this example, a low
1 LTC4230* 2 3 4 5 6 19 18 17 VCC2 16 RX ON 15 GND 14 13 12 VIAS TO GND PLANE Z CX 7 8 9 SNUBBER NETWORK VCC2 20
W
U
U
VOUT
NOTE: DRAWING IS NOT TO SCALE! USE SIMILAR TECHNIQUES FOR VCC1 AND VCC3 *ADDITIONAL DETAILS OMITTED FOR CLARITY
4230 F21
Figure 21. Recommended Layout for Transient Protection Devices
TransZorb is a registered trademark of General Instruments, GSI.
4230f
29
LTC4230
Z1 CX1 100nF RSENSE2 0.007 M2 IRF7413 Z2 CX2 100nF RSENSE3 0.007 M3 IRF7413 Z3 CX3 100nF RX3 10 RX2 10
RX1 10
COUT1
VCC2 2.5V
LONG
+
VOUT2 2.5V 5A COUT2
APPLICATIO S I FOR ATIO
VCC3 1.8V
LONG
+
VOUT3 1.8V 5A COUT3 P OR SYSTEM LOGIC
VCC1 10k 6 VCC1 SENSE 1 GATE 1 VCC2 SENSE 2 GATE 2 VCC3 M4 15 ON VCC1 7 8 16 17 18 5 4 SENSE 3 10k R5 10k
VCC1 3 GATE 3 FB3 1 R8 5.1k R9 12k RESET 3 13 FAULT LTC4230 GND RESET 2 RESET 1 19 9 R12 18k FILTER 11 TIMER 12 CFILTER 15pF CTIMER 0.1F FB1 10 R13 12k 14 2 R10 11k FB2 20 R7 10k
MASTER RESET
ON/OFF
SHORT
3-INPUT NOR GATE
FAULT
SHORT
R4 10k OPTIONAL
GND
LONG
R11 12k
R6 10k
R5 10k
VCC1 6.2V Z5 Z6
VCC2
VCC3
M4: 2N7002LT1 Z1, Z2, Z3: SMAJ10 Z4, Z5, Z6: 1N4691
NOTE: FOR ANY VCCn > 7.7V, THE Z4 LTC4230 IS IN OVERVOLTAGE PROTECTION MODE, FAULT IS PULLED LOW
4230 F22
4230f
Figure 22. LTC4230 High Side Overvoltage Protection Implementation
U
W
U
U
30
RSENSE1 0.007 M1 IRF7413
BACKPLANE CONNECTOR (FEMALE) VOUT1 3.3V 5A
PCB EDGE CONNECTOR (MALE)
VCC1 3.3V
LONG
+
LTC4230
APPLICATIO S I FOR ATIO
bias current 1N4691 zener diode is chosen to protect the system. Here, the zener diode is connected from VCC to the LTC4230's FILTER pin. If the input voltage to the system is greater than 6.8V during start-up, the voltage on the FILTER pin is pulled higher than its 1.19V threshold. As a result, the GATEn pin is not allowed to ramp and the second timing cycle will not commence until the supply overvoltage condition is removed. Should the supply overvoltage condition occur during normal operation, internal control logic would trip the electronic circuit breaker and the GATE would be pulled to ground, shutting off the external pass transistor. If a lower supply overvoltage threshold is desired, use a zener diode with a smaller breakdown voltage. A timing diagram for illustrating LTC4230 operation under a high side overvoltage condition is shown in Figure 23. The start-up sequence in this case (between Time Points 1 and 2) is identical to any other start-up sequence under normal operating conditions. At Time Point 2, the input supply voltage causes the zener diode to conduct thereby forcing VFILTER > 1.19V. At Time Point 3, FAULT is asserted low and the TIMER pin voltage ramps down. At Time Point 4, the LTC4230 checks if VFILTER < 1.19V. FAULT is asserted low (but not latched) to indicate a start-up failure. Only if the input overvoltage condition is removed before Time Point 5 does the start-up sequence resume at the second timing cycle. At this point in time, the GATEn pin voltage is allowed to ramp up, FAULT is pulled to logic high and the circuit breaker is armed. Should, at any time after Time Point 5, a supply overvoltage condition develop (VFILTER > 1.26V), the electronic circuit breaker will trip, the GATEn will be pulled low to turn off the external MOSFET and FAULT will be asserted low and latched. Low Side (Output) Overvoltage Protection A zener diode can be used in a similar fashion to detect/ protect the system against a supply overvoltage condition on the load (or low) side of the pass transistor. In this case, the zener diode is connected from the load to the LTC4230's FILTER pin, as shown in Figure 24. An additional diode, D1, prevents the FILTER pin from pulling low during
U
output short-circuit. Figure 25 illustrates the timing diagram for a low side output overvoltage condition. In this example, the LTC4230 can only sense the overvoltage supply condition after Time Point 5 and the GATEn pin has ramped up to its nominal operating value. After Time Point 5, a supply voltage fault occurs at the load and the zener diode conducts, causing VFILTER to increase. At Time Point 6, VFILTER is greater than 1.26V, the circuit breaker trips, GATE pulls to ground and FAULT asserts low and is latched. In either case, the LTC4230 can be configured to automatically initiate a start-up sequence. Please refer to the section on AutoRetry After a Fault for additional information. PCB LAYOUT CONSIDERATIONS For proper operation of the LTC4230's circuit breaker function, a 4-wire Kelvin connection to the sense resistors is highly recommended. A recommended PCB layout for the sense resistor, the power MOSFET and the GATE drive components around the LTC4230 is illustrated in Figure 26. In Hot Swap applications where load currents can reach 10A or more, narrow PCB tracks exhibit more resistance than wider tracks and operate at more elevated temperatures. Since the sheet resistance of 1 ounce copper foil is approximately 0.54m/square, track resistances add up quickly in high current applications. Thus, to keep PCB track resistance and temperature rise to a minimum, PCB track width must be appropriately sized. Consult Appendix A of LTC Application Note 69 for details on sizing and calculating trace resistances as a function of copper thickness. In the majority of applications, it will be necessary to use plated-through vias to make circuit connections from component layers to power and ground layers internal to the PC board. For 1 ounce copper foil plating, a good starting point is 1A of DC current per via, making sure the via is properly dimensioned so that solder completely fills any void. For other plating thicknesses, check with your PCB fabrication facility.
4230f
W
U
U
31
LTC4230
APPLICATIO S I FOR ATIO
CHECK FOR FILTER LOW (< VREF) CHECK FOR FAULT HIGH (> VREF + 50mV) CHECK FOR GATEn < 0.25V 12 34 IF THE OVERVOLTAGE GOES AWAY, THE SECOND CYCLE CONTINUES FAST COMPARATOR ARMED 5 6 SLOW COMPARATOR ARMED 7
ON
TIMER
RESET
GATEn VOUTn
FAULT
FAULT IS PULLED LOW (BUT NOT LATCHED), SINCE THE OVERVOLTAGE HAPPENED BEFORE THE END OF THE FIRST TIMING CYCLE
FILTER
4230 F23
Figure 23. High Side Overvoltage Protection Timing
32
U
GATEn POWER GOOD VOUTn FILTER < 1.19V
4230f
W
U
U
BACKPLANE CONNECTOR (FEMALE) RSENSE1 0.007 Z1 CX1 100nF RSENSE2 0.007 M2 IRF7413 Z2 CX2 100nF RSENSE3 0.007 M3 IRF7413 Z3 CX3 100nF P OR SYSTEM LOGIC VCC1 VCC1 R5 10k 6 VCC1 SENSE 1 GATE 1 VCC2 SENSE 2 GATE 2 VCC3 M4 15 ON RESET 3 13 FAULT LTC4230 GND RESET 2 RESET 1 VOUT1 VOUT3 6.2V Z5 D1 Z6 FILTER 11 CFILTER 15pF TIMER 12 CTIMER 0.1F FB1 10 VOUT2 19 9 R12 18k R13 12k
4230 F24
PCB EDGE CONNECTOR (MALE) M1 IRF7413 VOUT1 3.3V 5A COUT1
RX1 10
VCC2 2.5V RX2 10
LONG
+
VOUT2 2.5V 5A COUT2
APPLICATIO S I FOR ATIO
VCC3 1.8V RX3 10
LONG
+
VOUT3 1.8V 5A COUT3
MASTER RESET 7 8 16 17 18 5 4 SENSE 3 3 GATE 3 FB3 1 R8 5.1k R9 12k 2 R10 11k FB2 20 R7 10k
10k 10k 14
ON/OFF
SHORT
3-INPUT NOR GATE
VCC1 R4 10k OPTIONAL
FAULT
SHORT
GND
LONG
R11 12k
R6 10k
R5 10k
D1: 1N4148 M4: 2N7002LT1 Z1, Z2, Z3: SMAJ10 Z4, Z5, Z6: 1N4691
NOTE: FOR ANY VOUTn > 8.4V, THE Z4 LTC4230 IS IN OVERVOLTAGE PROTECTION MODE, FAULT IS PULLED LOW
LTC4230
33
4230f
Figure 24. LTC4230 Low Side Overvoltage Protection Implementation
U
W
U
U
VCC1 3.3V
LONG
+
LTC4230
APPLICATIO S I FOR ATIO
CHECK FOR FILTER LOW (< VREF) CHECK FOR FAULT HIGH (> VREF + 50mV) CHECK FOR GATEn < 0.25V 12 FAST COMPARATOR ARMED 3 45 6 7 CHECK FOR TIMER < 0.3V 8 9
ON 1.234V
TIMER
GATEn VOUTn
RESETn
FAULT
FILTER
FILTER < 1.26V
Figure 25. Low Side Overvoltage Protection Timing
34
U
FILTER < 1.19V
4230 F24
W
U
U
4230f
LTC4230
APPLICATIO S I FOR ATIO
CURRENT FLOW TO LOAD
SENSE RESISTOR (RSENSE) D D W D D
TRACK WIDTH W RGX* VIA TO GNDPLANE 5.1k CGX*
LTC4230**
CTIMER CURRENT FLOW TO LOAD
W
NOTE: DRAWING IS NOT TO SCALE! USE SIMILAR TECHNIQUES FOR VCC1 AND VCC2
Figure 26. Recommended Layout for LTC4230 RSENSE, Power MOSFET and Feedback Network
APPE DIX
Table 4 lists some current sense resistors that can be used with the circuit breaker. Table 5 lists some power MOSFETs that are available. Table 6 lists the web sites of several
Table 4. Sense Resistor Selection Guide
CURRENT LIMIT VALUE 1A 2A 2.5A 3.3A 5A 10A PART NUMBER LR120601R050 LR120601R025 LR120601R020 WSL2512R015F LR251201R010F WSR2R005F DESCRIPTION 0.05 0.5W 1% Resistor 0.025 0.5W 1% Resistor 0.02 0.5W 1% Resistor 0.015 1W 1% Resistor 0.01 1.5W 1% Resistor 0.005 2W 1% Resistor MANUFACTURER IRC-TT IRC-TT IRC-TT Vishay-Dale IRC-TT Vishay-Dale
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
POWER MOSFET SO-8 G S S S W CURRENT FLOW TO LOAD
W
8 13
U
U
10 11
9 TIMER 12
7 GND 14
6 15
5 VCC3 16
4 SENSE 3 17
3 GATE 3 18
**ADDITIONAL DETAILS OMITTED FOR CLARITY *OPTIONAL COMPONENTS
2 RESET 3 19
1 FB3 20
12k
4230 F26
U
manufacturers. Since this information is subject to change, please verify the part numbers with the manufacturer.
4230f
35
LTC4230
APPE DIX
Table 5. N-Channel MOSFET Selection Guide
CURRENT LEVEL (A) 0 to 2 2 to 5 5 to 10 10 to 20 PART NUMBER MMDF3N02HD MMSF5N02HD MTB50N06V MTB75N05HD DESCRIPTION Dual N-Channel SO-8, RDS(ON) = 0.09, CISS = 455pF Single N-Channel SO-8, RDS(ON) = 0.025, CISS = 1130pF Single N-Channel DD Pak, RDS(ON) = 0.028, CISS = 1570pF Single N-Channel DD Pak, RDS(ON) = 0.0095, CISS = 2600pF MANUFACTURER ON Semiconductor ON Semiconductor ON Semiconductor ON Semiconductor
Table 6. Manufacturers' Web Sites
MANUFACTURER TEMIC Semiconductor International Rectifier ON Semiconductor Intersil WEB SITE www.temic.com www.irf.com www.onsemi.com www.intersil.com MANUFACTURER IRC-TT Vishay-Dale Vishay-Siliconix Diodes, Inc. WEB SITE www.irctt.com www.vishay.com www.vishay.com www.diodes.com
PACKAGE DESCRIPTIO
0.015 0.004 x 45 (0.38 0.10) 0.007 - 0.0098 (0.178 - 0.249) 0.016 - 0.050 (0.406 - 1.270) 0 - 8 TYP
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PARTS
PART NUMBER LTC1421 LTC1422 LT1641-1/LT1641-2 LTC1642 LTC1644 LTC1647 LTC4211 LT4250L/LT4250H LTC4251 DESCRIPTION 2-Channel Hot Swap Controller Single Channel Hot Swap Controller in SO-8 Positive Voltage Hot Swap Controller Single Channel Hot Swap Controller PCI Hot Swap Controller Dual Channel Hot Swap Controller Single Hot Swap Controller with Multifunction Current Control Negative Voltage Hot Swap Controllers in SO-8 - 48V Hot Swap Controller in SOT-23 COMMENTS 24-Pin, Operates from 3V to 12V and Supports - 12V Operates from 2.7V to 12V Operates from 9V to 80V 16-Pin, Overvoltage Protection to 33V 3.3V, 5V and 12V, 1V Precharge, PCI Reset Logic 8-Pin, 16-Pin, Operates from 2.7V to 16.5V 2.5V to 16.5V, Similar Features as LTC4230 Operates from - 20V to -80V, Active Current Limiting -15V to -100V, Active Current Limiting
4230f LT/TP 0702 2K * PRINTED IN USA
36
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
U
U
GN Package 20-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
0.337 - 0.344* (8.560 - 8.737) 0.053 - 0.068 (1.351 - 1.727) 0.004 - 0.0098 (0.102 - 0.249) 20 19 18 17 16 15 14 13 12 11 0.058 (1.473) REF
0.008 - 0.012 (0.203 - 0.305)
0.0250 (0.635) BSC
0.229 - 0.244 (5.817 - 6.198)
0.150 - 0.157** (3.810 - 3.988)
1
23
4
56
7
8
9 10
GN20 (SSOP) 1098
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2001

▲Up To Search▲

Price & Availability of LTC4230

	To Download LTC4230 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .